Dynamic Random Access Memory (DRAM) typically uses several voltages that are generated internally to the DRAM. Some of the voltages are regulated out of the supply voltage VDD or Vint, if they are within the range VDD–VSS. Voltages with targets outside of the range VDD–VSS are typically pumped either out of VDD for a voltage higher than VDD (e.g., boosted word line voltage (VPP)) or out of VSS for a voltage lower than VSS (e.g., back bias voltage (VBB) for the array transistor).
The negative word line low voltage (VNWLL), which is the negative voltage for the word lines, and VBB are typically generated independently. The requirements for VNWLL and VBB are inverse. During power-up, VBB requires large drive capability for charging large parasitic decoupling capacitances between VBB and the plate voltage (VPL), between VBB and the bit line equalization voltage (VBLEQ), and between VBB and VNWLL. After power-up, VBB requires small drive capability since no significant leakage occurs. During power-up, VNWLL requires a small drive capability for charging parasitic decoupling capacitances between VNWLL and VBLEQ and between VNWLL and VBB. After power-up, VNWLL requires large drive capability for precharging the word lines during the active state.
The main task during power-up is to optimize the VPL and VBLEQ ramps to positive voltages and the VBB and VNWLL ramps to negative voltages within the defined specification of 200 μs for commodity DRAM or 150 μs for CellularRAM for every value of VDD, process case variation, and temperature. During power up, the capacitance network between VPL, VBLEQ, VBB, and VNWLL is charged. VPL and VBLEQ are charged on the positive side, and VBB and VNWLL are charged on the negative side. Because of the capacitance coupling, any rise in VPL or VBLEQ raises VBB and VNWLL to positive voltages with VBB or VNWLL floating. Therefore, typical DRAM includes discharge devices that limit any potential increase of VBB and VNWLL. Typically, VPL and VBLEQ operate with reduced drive capability during power-up in order to limit any VBB or VNWLL increase. This reduced drive capability during power-up, however, may result in a longer power-up time.
Typically, DRAM chips have an independent pump system for VBB and VNWLL and discharge devices to limit any potential VBB or VNWLL increase. In addition, the drive capability for VPL and VBLEQ may be adjusted to limit any potential VBB or VNWLL increase. For typical DRAM chips, several VBB pumps are needed for power-up, but after power-up only a small VBB pump is needed to balance the small leakage. Typical DRAM chips use a large chip area for the several VBB pumps and discharge devices that are only used during power-up.